I have a DUT with 2 Masters (M0 and M1) and 2 Slaves (S0 and S1). Ideally, M0 should be connected to S0 and M1 to S1.
But let’s suppose due to some design issues M0 got connected to S1 and M1 to S0, how can I catch such kind of error?
In reply to sfenil1804:
The common scenario is that you do not have dedicated connections between master and slave, ie. MO connected to SO and M1 connected to S1. The bus protocol describes how this has to be handled.