Verification of parametrized dut

UVM
1

Hi all,

What are different approaches to verify a parameterized DUT.

Lets say we have a DUT:

module dut                                                                     
#
(
   parameter  PARAMETER1 = 2,
   parameter  PARAMETER2 = 10,
   parameter  PARAMETER3 = 8,
)
(
   input  logic   clk ,
   input  logic   rstn ,
   .... );
endmodule

Now the DUT can be configured in several ways using these parameters. The DUT interface looks different for different set of parameters. What are some scalable and configurable approaches for this type of verification. Any inputs or pointers are much appreciated.

Thanks in advance

2

There are infinite combinations of the three parameter values that one could assign to the DUT. Verifying all these combinations is not possible. Morevor it would be a waste of verification resources.

In my opinion, we have to figure out the exact set of parameter values that will be set for the DUT and only verify these values.

For example if there are two instances of this dut in the final SOC.

dut#(3,5,6) dut_inst1;
dut#(4,5,8) dut_inst2;

I would focus my verfication efforts on these two sets of parameter values.

3

In reply to yasaswi93:

Hi all,
What are different approaches to verify a parameterized DUT.
Now the DUT can be configured in several ways using these parameters. The DUT interface looks different for different set of parameters. What are some scalable and configurable approaches for this type of verification. Any inputs or pointers are much appreciated.
Thanks in advance

I guess you want to disribute the parameters to the DUT and also to the UVM environment. Right?
And you might have a certain legal values for your parameters. Then you can randomize these parameters with respect to your constraints and dstribute them to both, the DUT and the environmen.