Uvm_reg access methods: parent argument?

UVM
1

For some reason we have never passed anything to it (defaulting in null), whilst most code I see uses for example

reg.write(status,32'h0, .parent(this));

What is the purpose of the parent argument?

2

In reply to NiLu:
That is the parent sequence. A register access starts a sequence and passed the parent to the access sequence. Parent/child sequence relationships can be useful for debugging, and also for more advanced features like arbitration, locking, etc.

3

In reply to dave_59:

So this is the same as when you have hierarchical sequences, where you also pass the parent?

4

In reply to NiLu:
Yes.