The `uvm_info in sequence did not print in my test

UVM
1

I started a “dphy_hs_sequence” in main_phase of a virtual sequencer. with rasie and drop objection in pre_body and post_body in this way;

  virtual task pre_body();
    uvm_phase phase;
    super.pre_body();
    phase = starting_phase;
    if(phase!=null) begin
      phase.raise_objection(this);
    end
  endtask: pre_body

I also start a “axi_snps_slave_sequence” in run_phase on another sequencer, without raise or drop objection, to serve as a AXI slave sequence. The axi_snps_slave_sequence is like this

class axi_snps_slave_sequence extends svt_axi_slave_base_sequence;
  virtual task body();
   `uvm_info("axi_snps_slave_sequence", "Entered ...", UVM_NONE)
    forever begin
      /*add bvaid delay for each transaction*/
    end
  endtask
endclass

The actions in forever loop take effects, the bvaid has delay on waveform. However, the "

`uvm_info("zeku_axi_snps_slave_sequence", "Entered ...", UVM_NONE)

" did not print. Could you please tell my why body task skip the `uvm_info and directly jump into the for loop?

My test is like this:

class csi_dphy_delay_response_test extends csi_base_test;
  function new (string name = "csi_dphy_delay_response_test",uvm_component parent = null);
    super.new(name, parent);
  endfunction : new
  `uvm_component_utils(csi_dphy_delay_response_test)

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    uvm_config_db#(uvm_object_wrapper)::set(this, "csi_env.vsqr.main_phase", "default_sequence", dphy_hs_sequence::type_id::get());
    uvm_config_db#(uvm_object_wrapper)::set(this, "csi_env.axi_slv.vip.slave[0].sequencer.run_phase", "default_sequence", axi_snps_slave_sequence::type_id::get());
  endfunction
endclass
2

In reply to Yuankun:

Could you please show some more code.
Two things I want to mention already:
(1) a sequence should never run in a forever loop, because it will never come to an end
(2) You are mixing main_phase and run_phase which might end up in a catastrophe.