I have a query regarding creating a sequence item.
How do you decide what fields will be included in sequence item?
For example, a DUT has two interfaces, one is AHB and other is AXI-S. These interface include control signals and data and address signals.
The data that is useful for DUT is tdata from AXI interface and write data (hwdata) from AHB interface.
How do you decide whether all signals of an interface will be part of item or some signals can be skipped?
If I have to skip control signals, then from where I will drive those control signals onto the interfaces?
The physical pins on the DUT interface are defined as part of the SystemVerilog interface for that agent. The data that will get passed through those pins is defined as part of the transaction class for the agent.
e.g. you might want to send 32 bits of data across an interface.
So in the transaction class you would define a data member something like
rand bit [31:0] tx_data;
The protocol will determine how you send those 32 data bits.
e.g.
You might send the data serially through a single data pin
You might send the data in parallel, via a single write operation, across a 32 bit data bus (with control signals)
You might send the data via 4 x sequential write operations across an 8 bit data bus (with control signals)
Typically for your scenario, you would create 2 separate agents;
one for AHB and the other for AXI-S
Each agent will have an interface which describes the pins required for that particular proptocol
Each agent will also have it’s own transaction class which defines the data members required for that protocol.
That makes the agents more reusable for other designs using AHB or AXI-S
So,
1 Keep the 2 interfaces separate and design an AHB agent and a AXI-S agent
2. Separate the physical pins from the transaction data to be sent across each interface
The actual query was as AHB consists of several signal, for example
reset
addr
write
wdata
rdata
ready
trans
resp
…etc
will AHB comprise of all of the these pins as sequence item?
The thing I am confused about is that some signals here represent actual data (wdata, rdata) which is exchanged between UVM component and DUT through interface. But several other signals are control signals which tell driver when to send and when not to send data to the interface.
Some people say full interface will be part of item, some do it differently. So, I am reiterating my question, how does one decide whether full interface signals will be part of item as fields or fewer signals?
interface ahb_if
(
input tri hclk,
input tri hresetn,
inout tri [31:0] haddr,
inout tri [15:0] hwdata,
inout tri [1:0] htrans,
inout tri [2:0] hburst,
inout tri [2:0] hsize,
inout tri hwrite,
inout tri hsel,
inout tri hready,
inout tri [15:0] hrdata,
inout tri [1:0] hresp
);
and here is the start of transaction class
class ahb_transaction extends uvmf_transaction_base;
`uvm_object_utils( ahb_transaction )
rand ahb_op_t op ;
rand bit [15:0] data ;
rand bit [31:0] addr ;
From the the sequence item point of view, you want to randomize
(a) is it a READ or a WRITE operation : this is ‘op’ in the above example
(b) the data
(c) the address
If doing a read, then the ‘data’ field will get populated with the actual read data that your agent monitor detects.
This AHB example is part of the UVM Framework base examples.
You can download the UVM Framework (inclusing this example) from the Verification Academy site.
Look inside this directory to find the agent source code (including the interface and the transaction class)
UVMF_2022.3\base_examples\verification_ip\interface_packages\ahb_pkg\src
To answer this question in a more broad sense, the sequence_item is a more like a high level
instruction (e.g, read the value at address 3000). The driver is supposed to take this high
level instruction and convert it to pin wiggles on the AHB interface signals. (12 signals in
your example).
it is a very bad idea to design your sequence_item with 12 variables