I am trying to find a way to selectively skip the reg2bus in the adapter when uvm register write is called.
Thanks,
In reply to dave_59:
There are 2 modes. In mode 1 the register write happens through the master VIP(normal reg adapter flow) and in mode 2 it’s done by some other processor. I am trying to use the same flow for both mode, so in mode 2 all the register address/data are pushed to a queue. The queue is used to do the programming. So the requirement in mode 2 is when register write happens only the queue should be populated but the transactions should not go through the adapter.
In reply to KARTHIKESAN NATARAJAN:
I do not understand how mode 2 should work. Are you forcing the registers in the DUT or what do you mean with populating?