I have a requirement in which UVC does the random stimulus to write into some memory address .
and the test case which is written in C will validate whether the memory read from that address is holding the same value which is written in UVC random stimulus . now is it possible to avoid the memory read to be done in the test case , by populating the C structure from UVC using DPI_C and access the same structure in test case which is written in C language ?
Note : the test case , which is written in C will be converted into .hex file which will be directly given to the processor
In reply to Nirmal Solomon:
I think you may be mixing up abstractions. If the test case is being converted to a hex file, then you are no longer dealing with C code — you now have machine code. What are the processor and memories modeled with? If not Verilog, then how is it linked into the simulation?
sorry the above question was misleading .
Can I define a C structure which will be populated from system verilog using DPI_C ?
and make this C structure points to specific memory location ?!
Idea is to access this same structure using scatter file mapping in the simulation time
In reply to Nirmal Solomon:
The answer is probably yes, but I still think you are mixing abstractions. You can certainly create data in SystemVerilog and move it to a location accessible by your C code.