UVM RAL

UVM
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1

What is the meaning of mirrored values and Desired values in UVM register Abstraction layer?

2

Mirrored values in the testbench are copies of DUT register values observed by looking at transactions on the bus connected to the DUT(frontdoor), or looking at signals directly inside the DUT(backdoor). Your testbench uses the mirrored values for quick access to make decisions on stimulus to the DUT and for the scoreboard to make decisions on expected results.

Desired values of registers in the testbench is a way to change the values of registers in the DUT. Frontdoor access will generate stimulus to set the register in the DUT, and backdoor access will set the registers directly without any stimulus.

An easy way to create a test is to set all the desired registered values and see that the mirrored values get updated to match the desired.

3

In reply to dave_59:

Thanks Dave. You mean to say,
[] Mirrored values are expected values of registers to check the correctness of DUT registers(Actual Value)
[] Desired values are the values of register during write transaction thorugh frontdoor/backdoor access.

Can you please tell me, are the above statements correct according to your answer?

Thanks in advance

4

In reply to sudheer:

Yes, except that the UVM uses the term predicted in contrast to expected for the mirrored values. Expected implies correctness which is the task for the scoreboard to determine.

5

In reply to dave_59:

Thanks Dave. I had more question regarding use of scoreboard when UVM Register Abstraction layer is implemented.

Mirror task is used to check the functionality of registers. Then what is the use of scoreboard to check the registers functionality?

6

In reply to sudheer:

You may want to take a look at this seminar Introduction to UVM Registers | UVM Recipe of the Month | Verification Academy
as well as the follow-up More UVM Registers | UVM Recipe of the Month | Verification Academy

7

In reply to dave_59:

In read & write access method, The doubt is:
The base sequence data variable is randomized & written to the selected register (Lets say for 2 registers i.e. reg 1 = 5c330b000499b08f (64 bit by default) & reg 2 = e7ba198b085c2d61 (64 bit by default)).

Then the register handle is shuffled & get() method is used to copy the mirrored value into ref_data.
(For instance: ref_data for reg 1 (8-bit – with “RO” access) is 8f & ref_data for reg 2 (8-bit) is 0 (because of “RO” access))

& at last ref_data is to be compared against the real h/w value via the read() method.
(So now the ref_data is same as above and data is 0 for both the registers)

Here what is the real h/w value, mirrored value and desired value?

Any suggestion and help would be greatly appreciated!

8

Why FATAL Error came …

UVM_INFO test.sv(42) @ 0: uvm_test_top [spi_reg_wr_rd_ral] Test hierarchy is below: -------------------------------------------------------------------
Name Type Size Value

uvm_test_top spi_reg_wr_rd_ral - @462
env spi_env - @1439
reg_predictor uvm_reg_predictor #(spi_tx) - @1477
bus_in uvm_analysis_imp - @1489
reg_ap uvm_analysis_port - @1498
sagent spi_agent - @1460
aport_spi uvm_analysis_port - @1468
drv spi_driver - @1679
rsp_port uvm_analysis_port - @1696
seq_item_port uvm_seq_item_pull_port - @1687
mon spi_mon - @1539
ap uvm_analysis_port - @1547
sqr spi_sqr - @1556
rsp_export uvm_analysis_export - @1564
seq_item_export uvm_seq_item_pull_imp - @1670
arbitration_queue array 0 -
lock_queue array 0 -
num_last_reqs integral 32 'd1
num_last_rsps integral 32 'd1
sbd spi_sbd - @1507
imp_drv uvm_analysis_imp_sent_pkt - @1524
imp_mon uvm_analysis_imp_rcvd_pkt - @1515

UVM_INFO test.sv(71) @ 0: uvm_test_top [run phase ] basic read wr test
UVM_FATAL /lin_tools/synopsys/vcs_mx_J-2014.12-sp3/etc/uvm-1.1/seq/uvm_sequencer_param_base.svh(295) @ 0: uvm_test_top.env.sagent.sqr [sqr] send_request failed to cast sequence item. User type = uvm_reg_item

— UVM Report Summary —

** Report counts by severity
UVM_INFO : 14
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 1
** Report counts by id
[Connect phase agent.sv] 1
[RNTST] 1
[SPI_AGENT] 1
[SPI_ENV] 4
[run phase ] 1
[spi_agent] 1
[spi_base_test] 2
[spi_driver] 1
[spi_reg_wr_rd_ral] 1
[sqr] 1
[wr_rd_test Main ] 1
$finish called from file “/lin_tools/synopsys/vcs_mx_J-2014.12-sp3/etc/uvm-1.1/base/uvm_report_object.svh”, line 292.
$finish at simulation time 0
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.610 seconds; Data structure size: 0.5Mb
Wed Dec 30 17:25:15 2015