UVM Pipelined driver synchronisation

UVM
1

Hello all,

I’m currently working on pipelined driver implementation for AHB bus and encountering few issues.

task do_pipelined_transfer;
  m_seq_item req; 
  forever begin
    pipeline_lock.get();
    seq_item_port.get(req);
    accept_tr(req, $time);
    void'(begin_tr(req, "pipelined_driver"));
    MBUS.MADDR <= req.MADDR;
    //other data and control signals
    @(posedge MBUS.MCLK);
    while(!MBUS.MRDY == 1) begin
      @(posedge MBUS.MCLK);
    end // End of command phase:
   pipeline_lock.put();   
    if(req.MREAD == 1) begin //  data phase
     //read data phase
    end
    else begin
      MBUS.MWDATA <= req.MWDATA;
      @(posedge MBUS.MCLK);
      while(MBUS.MRDY != 1) begin
        @(posedge MBUS.MCLK);
      end
      req.MRESP = MBUS.MRESP;
    end    
    seq_item_port.put(req); // Return the request as a response
    end_tr(req);
  end
endtask

When I’m sending in my 1st sequence item it completes the address phase and after the semaphore is released enters the data phase. Say req.MREAD = 0 and enters the “write” condition. After executing the line “MBUS.MWDATA <=req.MWDATA”, the next few lines where we assign the response(MRESP) doesn’t take place. It is in the same clock edge that the address phase of second sequence item takes place. Without completing the first seq_item’s data phase, the control immediately gets transferred to the address phase of the second item.
(@(posedge MBUS.MCLK); //// These lines are not executed for the 1st seq_item.The first seq_item doesn’t enter through this part of the code.
while(MBUS.MRDY != 1) begin
@(posedge MBUS.MCLK);
end
req.MRESP = MBUS.MRESP;
This happens only for the first seq_item and all the seq_items to follow works fine.
Is there any way to synchronize the two data & command threads and wait till the complete data phase is done for the 1st seq item?

Thanks in advance !