Uvm methodology

UVM
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Hi, one of my interviewer is asking is there any drawbacks in UVM methodology?
I check the answer for above question, in Cracking Digital VLSI Verification Interview: by Ramdas.
The answers is
With increasing adoption of UVM methodology in the verification industry, it should be clear that the advantages of UVM overweight any drawbacks.
1)For any one new to the methodology, the learning curve to understand all details and the library is very steep.
2)The methodology is still developing and has a lot of overhead that can sometimes cause simulation to appear slow or probably can have some bugs.
the above answer is considerable or not? is there any drawbacks in UVM methodology?

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In reply to anvesh dangeti:

My honest opinion is that you should answer this question based on your own experience with UVM.

The answer in the book mentioned is open ended; and not tailored to fit everyone. If i were the interviewer, i would follow up with questions like:

  1. what “some bugs” ?
  2. If simulation appears slower, why is it a problem with UVM methodology ?

The interviewer is trying to understand how you think. Answering it from your experience would be better than quoting an answer from a Q&A book.