What is the difference between uvm_hdl_deposit and $deposit? Do they see the path inputted in different ways?
In reply to Vaishnavi Balasubramanian:
Both $deposit and uvm_hdl_deposit do same work.
However, $deposit is not part of verilog / systemverilog standerd.
It is specific to EDA tool vendor only.
However, uvm_hdl_deposit is part of UVM standerd.
So, I will recommend you to always use uvm_hdl_deposit.
Thanks!