Using $sformatf for generating repeated name strings with different numerical

UVM
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1

Hi

I saw my code and it had a couple of repeated strings like uvm_analysis_imp_m0; uvm_analysis_imp_m1 ; and so on . Is there anyway we can generate this by using a for loop and $sformatf or any other way?

2

In reply to verific_engi:

SystemVerilog is a compiled language. There’s a big difference between “string” values and symbolic identifiers. You must compile source code into an executable form before you can execute statement that could manipulate any string values.

The best way of dealing with this is using arrays instead of variables with different identifier names. Or you can use editor commands or scripts to generate the needed code before compiling it.