Top level uvm_reg_block wrapper for multiple uvm_reg_blocks with different sequencer

UVM
,
1

Hi all,

I want to create a top-level uvm_reg_block wrapper which instantiates multiple block-level uvm_reg_blocks for different interfaces, hence I need to set separate sequencer for each instance of the block-level uvm_reg_block. I tried this:

// TOP LEVEL REG BLOCK
class top_level_reg_block extends uvm_Reg_block;

virtual function void build()
…
this.default_map = create_map (…);

this.block_a = block_a_type::type_id::create(block_a);
this.block_a.configure(this);
this.block_a.build();
this.block_a.lock_model();
this.default_map.add_submap(this.block_a.default_map, `BLOCK_A_OFFSET);

this.block_b = block_a_type::type_id::create(block_b);
this.block_b.configure(this);
this.block_b.build();
this.block_b.lock_model();
this.default_map.add_submap(this.block_b.default_map, `BLOCK_B_OFFSET);

endfunction: build

endclass

Env File :

top_level_reg_block rgb;

/// Build phase
…
rgb = top_level_reg_block::type_id:create(“rgb”);
rgb.build();
rgb.default_map.set_auto_predict(1);
rgb.default_map.set_base_addr(`BASE_ADDR);
rgb.default_map.reset();
rgb.reset();
rgb.lock_model();

//// Connect phase
…

rgb.block_a.default_map.set_sequencer (seq_a, adp_a);
rgb.block_b.default_map.set_sequencer (seq_b, adp_b);

I get FATAL Error whenever I try to access a register belongs to any of above Reg_block i.e. block_a or block_b.
UVM_FATAL @ 100.000 ns: reporter@@default_parent_seq [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in default_parent_seq

Further, I tried by setting the following:
rgb.default_map.set_sequencer(seq_a, adp_a);

This time it works but it always issues the requests on the seq_a.

I want to set both the sequencers so that it automatically determines which sequencer it needs to issue the request.

Any suggestions, please.

Thanks

2

In reply to vinodku1:

Create two maps in your top level rgb :-
a_map = create_map(“a_map”, 'h0, 1, UVM_LITTLE_ENDIAN);
b_map = create_map(“b_map”, 'h0, 1, UVM_LITTLE_ENDIAN);
default_map = a_map;

a_map.add_submap(block_a.default_map, {<>, 15’h0});
b_map.add_submap(block_b.default_map, {<>, 15’h0});

a_map.set_auto_predict(1);
b_map.set_auto_predict(1);

lock_model();

In your env where i suppose you build ral model :-
super.build_phase()
model = abcd_ral::type_id::create(“abcd_ral”);
model.build();
model.reset();
super.connect_phase(phase);

model.a_map.set_sequencer( a_agent_h.sequencer_h, a_adapter );
model.b_map.set_sequencer( b_agent_h.sequencer_h, b_adapter );

Now just make sure correct map is used when accessing any register.

uvm may throw some error when using multiple map, I had to modify a uvm source file to get around it.

3

In reply to nileshg:

Thanks for your help. It is working smoothly!

4

In reply to vinodku1:

Hi vinod,

I am facing same issue, can you let me know how you achived the changes as suggested by nilesh.

helps a lot.

regards,
nivas.