Tlm fifo blocking get giving wrong output

UVM
,
1

In following code :



`uvm_analysis_imp_decl(_in)

class my_scb extends uvm_scoreboard;
     `uvm_component_utils(my_scb)

     uvm_analysis_imp_in #(mon_tr, my_scb) in_export;

     uvm_analysis_port #(scb_tr) scb_port;
     uvm_analysis_export #(scb_tr) scb_export;
     uvm_tlm_analysis_fifo #(scb_tr) scb_fifo;
     
     function new(string name, uvm_component parent);
       super.new(name, parent);
     endfunction: new
 
     function void build_phase(uvm_phase phase);
       super.build_phase(phase);
       scb_port = new("scb_port", this);
       scb_export = new("scb_export", this);
       scb_fifo = new("scb_port", this);

     endfunction: build_phase
 
     function void connect_phase(uvm_phase phase);
          scb_port.connect(scb_export);
          scb_export.connect(fifo.analysis_export);
     endfunction: connect_phase
 
     task run();
          forever begin
               scb_tr my_scb_tr = new();
               fifo.get(my_scb_tr);
               `uvm_info("", "Got new scb tr", UVM_NONE);
          end
     endtask: run
 
     virtual function void write(mon_tr in_tr;);
         mon_tr my_mon_tr;
         scb_tr my_scb_tr = new();

         my_tr.copy(in_tr);

         convertMon2ScbTr(my_mon_tr, my_scb_tr); // converting tr

         scb_port.write(my_scb_tr);
         `uvm_info("", "Write to port done", UVM_NONE);
     endfunction: write
endclass: my_scb

Monitor is connected to scoreboard. And sending mon_tr.
I am seeing one peculiar case where prints are as follows on SAME TIME stamp:

Write to port done
Got new scb tr
Got new scb tr

Point to be noted, “Got new scb tr” are coming at same time stamp.
Here if I print scb tr along with “Got new scb tr” message, in first print tr data is incorrect while second print gets correct data.

I aren’t sure is this simulator issue or I am missing something very trivial in code.

2

A few points ::
(1) run should be replaced by run_phase() [ I believe its deprecated to use run() ]
(2) You have used scb_fifo and fifo interchangeably . It should be only scb_fifo
(3) Whats the point of having scb_port and scb_export ? .
Why don’t you directly connect ::

 scb_port.connect(scb_fifo.analysis_export) ;

You could even skip declaring :: **uvm_analysis_port #(scb_tr) scb_port;**  
Inside write function you can directly call ::


      scb_fifo.write(my_scb_tr);

(4) Calling scb_port.write(my_scb_tr) will essentially push the transaction in
tlm_analysis_fifo . So get() should be successful only once
( Only once per " Write to port done " display )