Timing constraints

UVM
1

How will achieve timing constraints in uvm

  1. time delay between the master and slave.
  2. Raising and falling time
    Tdelay = 2ns
    Tclk = 20 ns
    Reset = 200 micro sec
    Traise = 2ns
    Tfall = 2ns.

Please help me out to solve this problem.

2

In reply to mada saimanasa:

I dont think anything specific to UVM can help here. You need to take care of those delays in the clock and reset generation part and then use clocking blocks in your driver with appropriate input and output skews to properly drive the outputs and sample the inputs (directions w.r.t. the testbench).

Hope this helps.

3

In reply to ManjunathBhat:
Set up and hold time delay will take care using clocking by providing input skew and output skew.

4

In reply to mada saimanasa:

How will achieve timing constraints in uvm

  1. time delay between the master and slave.
  2. Raising and falling time
    Tdelay = 2ns
    Tclk = 20 ns
    Reset = 200 micro sec
    Traise = 2ns
    Tfall = 2ns.
    Please help me out to solve this problem.

On the RTL your timing constarint do not matter, but you should consider the clock frequency and the reset length. All the other timing information like Traise and Tfall are not relevant.

5

[i]In reply to chr_sue:[/

thank you chr_sue and ManjunathBhat.

So while verifying any design we only concentrate on clock and reset generation and set-up and hold times. Remaining timing constraints we are not concentrate right.

6

In reply to mada saimanasa:

You do not need to set setup and hold times. The clocking block is a construct to avoid races between DUT and testbench. It is not useful to define arrival times for signals.