Systemverilog binding with DUT's generate signals

UVM
, , ,
1

Hi,

New to SystemVerilog/UVM and hoping anyone can kindly help with this problem. Thanks in advance for any help. I have a SystemVerilog UVM testbench and would like to access the DUT internal signals written in VHDL. Please see below.

g0: for i in 0 to 7 generate
I4 : Component_A
port map( signalA => signalA);
end generate g0;

I want to access signalA in generate 1. Are these syntax below correct?

  1. Create an interface:
    interface DUT_Component_A_if
    (
    input logic signalA
    );
    endinterface: DUT_Component_A_if

  2. binding DUT
    bind TB_top.DUT.I1.I0.g0[1].I4 DUT_Component_A_if Probe_IF(.signalA(signalA));

  3. Put interface into the database
    uvm_config_db#(virtual DUT_Component_A_if)::set(null, “*”, “DUT_Inner_Signals”, TB_top.DUT.I1.I0.g0[1].I4.Probe_IF);

Compile passed with QuestaSim, but simulation ran with error: Error (suppressible): (vopt-7063) …/test_bench/src/DRFM_tb/DRFM_tb_lib/hdl/DRFM_TB_top.sv(337): Failed to find ‘Probe_IF’ in hierarchical name ‘/TB_top/DUT/I1/I0/g0[1]/I4/Probe_IF’.

2

In reply to sleeplycat:

Unfortunately there is no standard for communication between different standards. You need to read the user manual of your tool or contact your tool vendor directly. This Mentor sponsored forum is not for tool specific issues.

3

In reply to sleeplycat:

Hi,
New to SystemVerilog/UVM and hoping anyone can kindly help with this problem. Thanks in advance for any help. I have a SystemVerilog UVM testbench and would like to access the DUT internal signals written in VHDL. Please see below.
g0: for i in 0 to 7 generate
I4 : Component_A
port map( signalA => signalA);
end generate g0;
I want to access signalA in generate 1. Are these syntax below correct?

  1. Create an interface:
    interface DUT_Component_A_if
    (
    input logic signalA
    );
    endinterface: DUT_Component_A_if
  2. binding DUT
    bind TB_top.DUT.I1.I0.g0[1].I4 DUT_Component_A_if Probe_IF(.signalA(signalA));
  3. Put interface into the database
    uvm_config_db#(virtual DUT_Component_A_if)::set(null, “*”, “DUT_Inner_Signals”, TB_top.DUT.I1.I0.g0[1].I4.Probe_IF);
    Compile passed with QuestaSim, but simulation ran with error: Error (suppressible): (vopt-7063) …/test_bench/src/DRFM_tb/DRFM_tb_lib/hdl/DRFM_TB_top.sv(337): Failed to find ‘Probe_IF’ in hierarchical name ‘/TB_top/DUT/I1/I0/g0[1]/I4/Probe_IF’.

Because I do not know the details of your DUT I have simplified this and moved the generate into the SV-file.

DUT:

library ieee;
use ieee.std_logic_1164.all;

entity Component_A is
end Component_A;

architecture rtl of Component_A is
   signal signalA : std_logic;

begin
  signalA  <= '1';
end rtl;

SV top:

interface DUT_Component_A_if(input logic signalA);
endinterface: DUT_Component_A_if

module top;

genvar i;
for (i = 0; i <= 7; i++)
   Component_A DUT();

bind genblk1[2].DUT DUT_Component_A_if Probe_IF(.signalA(signalA));

endmodule

Each simulator has a specific naming for the generate instances. Here it is genblk. It might be different using another simulator. This is what you have to find out in your environment to complete your bind-construct.