Subsequencer object is not created in build_phase in virtual sequencers

This is a basic question on UVM.

I am looking into correct usage of Virtual sequencer and i see that in virtual sequencer, sub-sequencer’s handle are not created in build phase.

It is specified by environment using configuration database.

Why it is not build as done in commented out build_phase?

class vsequencer extends uvm_sequencer;
   `uvm_component_utils(vsequencer)
   tb_ahb_sequencer ahb_sqr;  //subsequencer handle
   tb_eth_sequencer eth_sqr;  //subsequencer handle 

   function new(string name, uvm_component parent);
     super.new(name, parent);
   endfunction

   //function void build_phase(uvm_phase phase);    //Why not build like this?
   //  ahb_sqr = tb_ahb_sequencer::type_id::create("ahb_sqr");
   //  eth_sqr = tb_eth_sequencer::type_id::create("eth_sqr");
   //endfunction

   function void end_of_elaboration_phase(uvm_phase phase);
     super.end_of_elaboration_phase(phase);
     if (!uvm_config_db#(tb_ahb_sequencer)::get(this, "", "ahb_sqr", ahb_sqr))
       `uvm_fatal("VSQR/CFG/NOAHB", "No ahb_sqr specified for this instance");
     if (!uvm_config_db#(tb_eth_sequencer)::get(this, "", "eth_sqr", eth_sqr))
       `uvm_fatal("VSQR/CFG/NOETH", "No eth_sqr specified for this instance");
   endfunction

endclass

In reply to gargneer:

You should never create a virtual sequencer component. The best approach is to have the handles to your sequencers as part of a base virtual sequence. You can then extend your virtual sequences from the base virtual sequence. When the virtual sequence is created in the test, you assign the virtual sequence handles from the agent’s sequencers in the environment.

Sequencers are UVM components which are created once per entire simulation.
Sequencers are created inside their corresponding agent and in order use them we need to point to the handles present inside the agent.

Hence, we can say creating the handles inside virtual sequencer build phase is not necessary or not allowed.

In reply to cgales:

I am not aware of this. Is there a reason you are saying that we should never create a virtual sequencer component?

In reply to gargneer:

Yes. You should never create a virtual sequencer component. Instead, assign the handles in the virtual sequence as I explained above. This reduces complexity in your environment, reduces the number of components you need to code/instantiate, and provides greater flexibility as you run your virtual sequence on a null sequencer. When you start your sequence and specify ‘null’ as the sequencer, UVM will create a sequencer for you automatically.