Hi,
I am writing a checker inside my sequence. Can I access RTL signals inside the sequence through the hierarchy? For example, In tb_top I can access dut signals through dut.signal_name, in the same manner, I want to access it inside the sequence. I don’t want to use get response and put response.
Thanks
In reply to Abhijeet Anand:
The use of SystemVerilog packages prevents you from using out of scope hierarchical references. This prevents direct signal access such as ‘tb_top.dut.signal_name’. You could use virtual interface handles, but it is highly recommended to only use virtual interfaces at the driver/monitor level.
You should create checkers/assertions in a separate module and bind them to the DUT at the appropriate level. Your sequences should only be used for stimulus generation and not design checking.