at first i Built a system-verilog environment
and to do the comparison between the refrence model and the data coming from the dut “sampled from the monitor”
the input data “generated from the stimulus generator” is sent to the refrence model to do the comparison
now i need to map this method into the UVM
iam confused between 2 choices
should i send the data from the sequencer or driver to the scoreboard/refrence Model
i searched and found something called passive and active agent and the passive one has a monitor class that sends to the refrence model
, could this monitor samples the inputs ?
Yes, the monitor samples the inputs to the DUT. This way is preferred for a couple of reasons.
First, there is no guarantee that the generated stimulus actually arrives at the DUT until the motor see it. This serves as an extra check depending on how complicated your stimulus generation is.
The idea behind the active/passive agent promotes re-use at multiple levels. If you are doing unit/block-level testing, you want to be able to switch between testbench generated stimulus and stimulus coming from another RTL. Having the monitor separate lets you have a passive agent that only monitors and does not depend on have the stimulus generator/driver active.
in case of not doing a block level testing
should i implement the passive agent that monitoring !
or i depend on the monitor in the active agent to monitor the inputs and outputs
and use this input in the refrence model !