Hi there,
With UVM 1.2 I am getting a warning that seems to be related to building a hierarchical register model. As soon as the build() method of 2nd regblock hierarchy is called, the following warning is issued:
UVM_WARNING /opt/synopsys/J-2014.12-SP1-1//etc/uvm-1.2/base/uvm_resource.svh(1421) @ 0: reporter [UVM/RSRC/NOREGEX] a resource with meta characters in the field name has been created “m_my_regmodel.sw_debug_regs”
When setting a breakpoint on the respective code line I see that the problem is related to the “.” (dot) in the sub-hierarchy uvm_reg_block**.**uvm_reg_map
- Is there any problem with using hierarchical uvm_reg_blocks in uvm 1.2?
- Is there any better way to build complex models with keeping a good structure?
Below the code of the register model I use to reproduce the warning:
class debug_uc_0_rc extends uvm_reg;
`uvm_object_utils(debug_uc_0_rc)
rand uvm_reg_field debug_uc_0_rf;
function new(string names = "debug_uc_0_rc");
super.new(names, 32, UVM_NO_COVERAGE);
endfunction
virtual function void build();
debug_uc_0_rf = uvm_reg_field::type_id::create("debug_uc_0_rf");
debug_uc_0_rf.configure(
.parent (this),
.size (32),
.lsb_pos (0),
.access ("RW"),
.volatile (0),
.reset (32'd0),
.has_reset (1),
.is_rand (0),
.individually_accessible (0));
add_hdl_path_slice(
.name( "reg_debug_uc_0" ),
.offset( 0 ),
.size( 32 ) );
endfunction : build
endclass
class sub_register_model extends uvm_reg_block;
`uvm_object_utils(sub_register_model)
rand debug_uc_0_rc debug_uc_0_reg;
uvm_reg_map sw_debug_map;
function new(string name = "sub_register_model");
super.new(name, UVM_NO_COVERAGE);
endfunction
virtual function void build();
debug_uc_0_reg = debug_uc_0_rc::type_id::create("debug_uc_0_reg");
debug_uc_0_reg.build();
debug_uc_0_reg.configure(this, null, "");
this.sw_debug_map = create_map("sw_debug_map", 'h0, 4, UVM_LITTLE_ENDIAN, .byte_addressing(0));
this.sw_debug_map.add_reg(debug_uc_0_reg, 32'h3e0 , "RW");
endfunction
endclass
class my_register_model extends uvm_reg_block;
`uvm_object_utils(my_register_model)
function new(string name = "wcu_register_model");
super.new(name);
endfunction
rand sub_register_model sw_debug_regs;
uvm_reg_map custom_regs_map;
function void build();
custom_regs_map = new("custom_regs_map");
custom_regs_map = create_map("custom_regs_map", 'h0, 4, UVM_LITTLE_ENDIAN, .byte_addressing(0));
sw_debug_regs = sub_register_model::type_id::create("sw_debug_regs", , get_full_name());
sw_debug_regs.configure(this, "");
sw_debug_regs.build();
sw_debug_regs.lock_model();
custom_regs_map.add_submap(this.sw_debug_regs.default_map, 'h0);
this.lock_model();
endfunction
endclass