I have an environment that instantiates a virtual sequencer (pcie_sqr) with a handle on a couple of sequencers (rc_sqr and ep_sqr) for a couple of agents (rc_agt and ep_agt).
All this is good and works as expected, the virtual sequence (write_then_read_vseq) is coordinating the execution of two sequences on those two agents.
Now the dut has added a mode of operation that needs to be “configured” through a serial interface, setting some registers with some values before the previously mentioned sequence could be started again. So I thought I could add an extra environment with the serial agent, hook up the register abstraction layer in the top environment and connect it to the serial interface sequencer.
At this point I’m a bit struggling. The register sequence needed to configure the dut is not run on a sequencer, but it performs register accesses which in turns are exchanged with the connected sequencer. So now if I want a top virtual sequence top_vseq that is coordinating the reg_config_vseq and the write_then_read_vseq but I do not know a) on which sequencer I should run top_vseq and b) how should it look like (meaning, which handles should it have).
Moreover I’m not really sure I know how would I start a uvm_reg_sequence, up to now I used to pass the regmodel handle to a virtual sequence and let it access registers directly, but if I want to separate my register access should I start it on a null sequencer? Uhm, if that’s the case I guess I got the answer to my questions above as well.
Well, hope someone could bring some clarity.