Register map : set_defaul_map is not working for multiple register maps

UVM
,
1

I am trying to create two register maps and then setting default map using “set_default_map” after adding registers. Then taking this register model instance in top-level register map where other maps are instantiated.

Here is snippet of my code.

class reg_block extends uvm_reg_block;
 // Now define address mappings
        spi_map = create_map("spi_map", 16'h0000, 2, UVM_LITTLE_ENDIAN);
        ahb_map  = create_map("ahb_map", 16'h0000, 2, UVM_LITTLE_ENDIAN);

     //Add registers into spi map 
        spi_map.add_reg(reg_1,16'h0,RO)
        spi_map.add_reg(reg_2,16'h0,RO)
      
      /Add registers into spi map 
        ahb_map.add_reg(reg_1,16'h0,RO)
        ahb_map.add_reg(reg_2,16'h0,RO)
 
       set_default_map(ahb_map);
       this.lock_model();
end reg_block

//top reg
package top_reg_pkg;

class top_reg_model extends uvm_reg_block;
        rand my_reg_block_c m_reg;
        rand uvm_mem        m_mem;        
        uvm_reg_map top_map;

        `uvm_object_utils(top_reg_model)

        virtual function void build();
            bit BYTE_ADDRESSING_OFF = 0;    // assign zero to byte_addressing to turn it off
            top_map = create_map( "top_map", 0, 2, UVM_LITTLE_ENDIAN, BYTE_ADDRESSING_OFF );
            m_reg = my_reg_block_c::type_id::create("m_reg", , get_full_name());
            m_reg.configure(this, "");
            m_reg.build();
            top_map.add_submap( ahb_map, 16'h8000 );
            top_map.add_submap( spi_map, 16'4000 );
     
            m_reg.set_default_map(m_reg.ahb_map);
            m_reg.lock_model();

            m_mem = new( "m_mem", `DATARAM_SIZE, 16 );  
            m_mem.configure( this, "" );
            top_map.add_mem( m_mem, `DATARAM_BASE ); 
            this.lock_model()
endfunction

endclass

endpackage

//In environment 

class my_env extends uvm_env

virtual function build_phase()

function build_phase()
 if( m_regmodel == null) begin
        m_regmodel = top_reg::type_id::create("m_regmodel");
        m_regmodel.build();
        m_regmodel.lock_model();
            // Set the regmodel object in the config_db so that it can be picked up by others
        uvm_config_db#(top_uvm_reg_block)::set( null, "", "top_uvm_reg_block", m_regmodel );
    end
endfunction 

function connect_phase
   m_regmodel.top_map.set_sequencer( spi_mst_agent.m_sqr, m_reg_adapter );
        // Setup the regmodel predictor
    m_reg_predictor.map     = m_regmodel.top_map;
    m_reg_predictor.adapter = m_reg_adapter;
        // Turn on/off auto prediction.
    m_regmodel.top_map.set_auto_predict(1);    
    
    m_ahb_predictor.map     = m_regmodel.top_map;
    m_ahb_reg_predictor.adapter = m_ahb_reg_adapter;

    m_regmodel.top_map.set_sequencer( m_ahb_agent.m_sequencer, m_ahb_reg_adapter );
    m_regmodel.m_reg.ahb_map.set_auto_predict(1);    

        // Connect the master monitor's analysis port to the predictor's bus_in port.
    m_spi_mst_agent.m_mon.m_ap.connect( m_reg_predictor.bus_in );
    m_ahb_agent.analysis_port.connect(m_ahb_reg_predictor.bus_in);
  
endfunction

In my Test class

  bit_bashtest_seq.model = m_env.m_regmodel.m_reg;
  bit_bashtest_seq.start(null);

somehow my test always takes spi_map as a default map even though i have set ahb_map as default map in reg-model.

In my test i see following message being printed.

Reading address 'h4000 via map “m_regmodel.m_reg.spi_map”…

When I comment all “spi_map.add_reg” for register model ,then only it is taking AHB MAP.

Can someone please let me know if I am missing anything here ? It’s bit urgent.