Register Abstraction Layer - reg_adapter

UVM
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1

Hi,

I would like to know the answers for the following questions,

  • Why we are using kind and command keyword in Reg_adapter
  • reg2bus will convert register transaction to bus transaction , why we are giving uvm_sequence_item outside of the argument

virtual function uvm_sequence_item reg2bus( const ref uvm_reg_bus_op rw );
jelly_bean_transaction jb_tx
= jelly_bean_transaction::type_id::create(“jb_tx”);

  if ( rw.kind == UVM_READ )       jb_tx.command = jelly_bean_types::READ;
  else if ( rw.kind == UVM_WRITE ) jb_tx.command = jelly_bean_types::WRITE;
  else                             jb_tx.command = jelly_bean_types::NO_OP;
  if ( rw.kind == UVM_WRITE )
    { jb_tx.sour, jb_tx.sugar_free, jb_tx.color, jb_tx.flavor } = rw.data;
  return jb_tx;

endfunction: reg2bus

virtual function void bus2reg( uvm_sequence_item bus_item,
ref uvm_reg_bus_op rw );
jelly_bean_transaction jb_tx;

  if ( ! $cast( jb_tx, bus_item ) ) begin
     `uvm_fatal( get_name(),
                 "bus_item is not of the jelly_bean_transaction type." )
     return;
  end
2

In reply to AravindLakshman:

Please look at the Verification Academy section on Register Adapters. It gives a clear and concise explanation of what the register adapters do and how to implement them.