Can anyone tell me the importance of REG Model in UVM testbench
UVM RAL is abstract layer for accessing registers in the RTL and performing various register related operations. For example, by using the RAL based approach, the user need not to know individual addresses, offsets and attributes of each individual field in the RTL. There are many more advantages also. Moreover, it is a highly reusable approach to make use of RAL at higher/SoC level of environments. Since it is a wide scope question, here is a brief about various components of RAL.
Going from low level to high level, firstly we create classes for individual fields in registers. Each field of the register is defined as a uvm_reg_field. The fields are configured in the build function.
The model of the any register is defined by extending the uvm_reg class. In a reg model, we take instance of each field in a register and apply default constraints to them.
The fields are then configured by using configure method. Here we assign the RW/RO/WO etc. attributes to each field in the register. Also the bit position offset, reset value, size of the field etc. are programmed in individual field classes.
The instance of reg is taken in a reg block where all the registers are instantiated and a register map is created with address offsets and attributes.
This is how each register map is created in a reg file. Moreover, there is an adapter which converts the transaction level object to the interface level object and vice-versa.
There are many more features and components available in RAL. Please go through UVM user guide and Cluelogic site for detailed information about UVM RAL.