I am facing an issue with uvm_config_db and need a clarification regarding the same. I have a requirement of probing the RTL and checking few signals in my test. I have assigned the signals to a tb bit and sent the bit using uvm_config_db. Below is the relevant part of the code which I wrote in my tb.
axi2apb_default_slave_intr = v5cpe_top_u.v5cpe_core.periphss.APB_DSLAVE.int_out;
I am seeing that the value I receive through the variable (axi2apb_default_slave_intr) is not changing with time.
My question: In this case, is a pointer to the variable axi2apb_default_slave_intr passed through uvm_config_db or is it the value of axi2apb_default_slave_intr at the start of build phase being sent. (I am getting this signal in my test during the build phase)
Thanks in advance