RAL W0 type register

UVM
1

I have constraint W0 type field in registers to 0 . When I call randomize of that registers that W0 type also gets randomize .

Example : Register ABC
AND fields inside are
L [ 2:0 ] R/w
M [ 3:0 ] R/W
N W0

Any idea why does W0 also gets randomize ?

2

In reply to MP:

Could you please explain what your objective is and how you are randomizing your register content.
IMO registers have dedicated alues and they are not randomized. BTW WO is not a constraint it is an access policy.