Actually i was working with the RAL so, in that the adapter have two functions
- reg2bus function
- bus2reg function
in both the functions we have the transaction class members/properties. Now i want to the see the values of those class members/properties for that i have used the “UVM_INFO” but i’m not getting any output in my transcript.
Now the question is that i need to see the predictor values and adapter values in my transcript for that i have used this UVM_INFO but i’m unable to see the output. how can we print the values of register model…?
can anyone help me out from this.?
regards,
Abhishek.E
In reply to abhishek403:
Of course can you print data from reg2bus or bus2reg to the simulation log-file using `uvm_info.
Did you check the verbosity of the commands reg2bus/bus2reg?
In reply to chr_sue:
ya, i have checked the verbosity. i don’t know exactly what’s happening and one more doubt is that i’m creating sequences and calling it the test this sequences is for uvm testbench and now i’m creating sequences for register model also, here i want to see the sequences details of my RAL model but i’m getting the details of my uvm testbench sequence details. if i’m worng please correct me
In reply to abhishek403:
Are you sure your RAL adapter has been created and is correctly connected.
With respect to the tests it is the common way to define in the test which sequence will be executed. Of course you’ll see any activity from the adapter only when you are running register sequences.
In reply to chr_sue:
No connection. Thanks for that
can you suggest me for learning the RAL, just like what is the purpose of the RAL,what can we achieve with RAL. why we need backdoor access…? something like that, i have gone through the cookbook for RAL model but its bit difficulty to understand the cookbook
In reply to abhishek403:
Today most designs have (status) registers. For this reason you have to verify them (access rights, reset vaues, access etc.). These registers are also used to evaluate simulation results or they are storing itsself certain functional values, like interrupts etc. If you do not have the RAL in your testbench you have alsways to perform a bus-cycle to get the values. This is veryx costly and time-consuming. The RAL can be accessed directly from your testbench to get the values making a simple get. The backdoor access makes the access to the register extremly simple, because you are lookin directly through the hierarchy of your design to the registers in your design. And it helps you verify registers with certain functionality, i.e RO or WO registers.