Parameterizing transaction

UVM
,
1

hi all,
when i am parametrizing my code like

in transaction:-

class transaction#(int iq_ctrl=7,int cw_ctrl=1) extends uvm_sequence_item;
`uvm_object_param_utils(transaction#(iq_ctrl,cw_ctrl))

typedef struct {
rand bit [0:((iq_ctrl120)-1)] data;
rand bit [0:((cw_ctrl8)-1)] word;
} d_basic_frame;
in driver:-

class driver#(int iq_ctrl=7,int cw_ctrl=1) extends uvm_driver#(transaction#(iq_ctrl,cw_ctrl));
`uvm_component_param_utils(driver#(iq_ctrl,cw_ctrl))

virtual cpri_interface vif_h;
transaction#(iq_ctrl,cw_ctrl) trans_h;

in test:-
class test #(int iq_ctrl=7,int cw_ctrl=1) extends uvm_test;
`uvm_component_param_utils(test#(iq_ctrl,cw_ctrl))

class p20 extends test#(1,1);
//class p20 extends test#(7,1);
uvm_component_utils(p20) function new(string name="p20",uvm_component parent); super.new(name,parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); ................... phase.drop_objection(this); endtask endclass :p20 //////////////// in sequencer/// class sequencer#(int iq_ctrl=7,int cw_ctrl=1) extends uvm_sequencer#(transaction#(iq_ctrl,cw_ctrl)); uvm_component_param_utils(sequencer#(iq_ctrl,cw_ctrl))

////////////////////in sequence////
class master_sequence#(int iq_ctrl=7,int cw_ctrl=1) extends uvm_sequence #(transaction#(iq_ctrl,cw_ctrl));
`uvm_object_param_utils(master_sequence#(iq_ctrl,cw_ctrl))
transaction#(iq_ctrl,cw_ctrl) trans; //

class p20 extends master_sequence;
`uvm_object_utils(p20)

function new(string name =“tx_ethernet_p20”);
super.new(name);
endfunction
task body();
…
endtask
endclass
///////////////////////
similarly for sequence, monitor,agent,environment.
interface,agent config, env config not parametrized.
//////////////////////////////////////////////////////////////
when i give
class p20 extends test#(7,1) (same value as set default) it runs perfectly.

error comes when i try to override and give:- class p20 extends test#(1,1); it shows UVM_FATAL @ 0: uvm_test_top.env_h.m_agent_h.seqr_h [seqr_h] send_request failed to cast sequence item.
for this eror…

i got the clue that in driver get_item(trans) is not working. as i put display there and get to know. but not getting how to solve

second query:- is it necessary to parametrize driver,monitor,sequence and all if i am parametrizing transaction.
in driver:-

class driver extends uvm_driver#(transaction#(iq_ctrl,cw_ctrl));
`uvm_component_utils(driver)

virtual cpri_interface vif_h;
transaction#(iq_ctrl,cw_ctrl) trans_h;
shows error that iq_ctrl,cw_ctrl not defined.

2

In reply to Er. Tripathi:

when i give
class p20 extends test#(7,1) (same value as set default) it runs perfectly.
error comes when i try to override and give:- class p20 extends test#(1,1); it shows UVM_FATAL @ 0: uvm_test_top.env_h.m_agent_h.seqr_h [seqr_h] send_request failed to cast sequence item.
for this eror…
i got the clue that in driver get_item(trans) is not working. as i put display there and get to know. but not getting how to solve

I’d try changing the following line:

class p20 extends master_sequence;

to this, so that the non-default values flow through to the transaction for the sequence

class p20 extends master_sequence#(int iq_ctrl=7,int cw_ctrl=1);

Also, you don’t show how you instantiate/build the driver, sequencer, sequence and other stuff. The values to bind for the parameters will need to flow through to all parameterized instances or the default will be used.

I think things could be cleaned up a bit and easier to read with some typedefs for the parameterized stuff. Could you parameterize the transaction by type and pass a typedef for the packed struct for the parameter? You might not need to parameterize everything else with the iq_ctrl and cw_ctrl if you do that – just parameterized with the transaction item type where needed.

3

In reply to jeremy.ralph:

hi
when i tried:-
class p20 extends master_sequence#(int iq_ctrl=7,int cw_ctrl=1);
it shows error

** Error: sequence.sv(298): near “iq_ctrl”: syntax error, unexpected IDENTIFIER, expecting ‘)’ or ‘,’

** Error: sequence.sv(298): Error in class extension specification.

one more thing:- if i write like this: and pass different values from test like 1,1… will this 32 be overwrite?
my_param_component #(.ADDR_WIDTH(32), .DATA_WIDTH(32))
m_my_p_component = my_param_component #(32,32)::type_id::create(“m_my_p_component”, this);

4

In reply to Er. Tripathi:

Could you please try

class p20 extends master_sequence#(iq_ctrl=7, cw_ctrl=1);

BTW you are doing quite strange and risky things. If you have to modify soemthing in your parameter list it seems you have to do this in all claases. Why do you need this?
What you are doing with the parameters in your sequencer definition?
I try to understand the story behind.

5

In reply to chr_sue:
hi,
i want to control number of bits sending from transaction to driver. i want this control is to take from test. as i decide in test, how many bits should go from transaction to driver.

in transaction:-

class transaction#(int iq_ctrl=7,int cw_ctrl=1) extends uvm_sequence_item;
`uvm_object_param_utils(transaction#(iq_ctrl,cw_ctrl))

typedef struct {
rand bit [0:((iq_ctrl120)-1)] data;
rand bit [0:((cw_ctrl8)-1)] word;
} d_basic_frame;

in test:-
class test #(int iq_ctrl=7,int cw_ctrl=1) extends uvm_test;
`uvm_component_param_utils(test#(iq_ctrl,cw_ctrl))

class p20 extends test#(1,1);
//class p20 extends test#(7,1);
`uvm_component_utils(p20)
function new(string name=“p20”,uvm_component parent);
super.new(name,parent);
endfunction
task run_phase(uvm_phase phase);
phase.raise_objection(this);
…
phase.drop_objection(this);
endtask
endclass :p20

6

In reply to Er. Tripathi:

You could do this simply without any parameter, using instead the config_db and setting the appropriate value from your test.
This is a safe and useful approach.

7

In reply to chr_sue:

this also shows error.
Error: sequence.sv(298): near “iq_ctrl”: syntax error, unexpected ‘#’ IDENTIFIER

8

In reply to chr_sue:

In reply to Er. Tripathi:
You could do this simply without any parameter, using instead the config_db and setting the appropriate value from your test.
This is a safe and useful approach.

please provide a hint for that.

9

In reply to Er. Tripathi:
Please find here a very simple example. It does not reflect the UVM hierarchy, but it shows the mechanisms.

package my_test_pkg;
`include "uvm_macros.svh"
import uvm_pkg::*;

class transaction extends uvm_sequence_item;
`uvm_object_utils(transaction)

rand bit data [];
rand bit word [];

int iq_ctrl = 8;
int cw_ctrl = 1;

function new (string name = "transaction");
   super.new(name);
   uvm_resource_db #(int)::read_by_name("", "iq", iq_ctrl);
   uvm_resource_db #(int)::read_by_name("", "cw", cw_ctrl);
   data = new[iq_ctrl*120];
   word = new[cw_ctrl*8];
endfunction   

endclass

class test extends uvm_test;

`uvm_component_utils(test)

function new(string name = "test", uvm_component parent = null);
  super.new(name, parent);
endfunction  

task run_phase (uvm_phase phase);
   transaction req;
   int iq = 10;
   int cw = 2;
   uvm_resource_db #(int)::set("*", "iq", iq);
   uvm_resource_db #(int)::set("*", "cw", cw);
   req = transaction::type_id::create("req");
   `uvm_info(get_type_name(), $psprintf("data_size = %0d", req.data.size), UVM_LOW)
   `uvm_info(get_type_name(), $psprintf("word_size = %0d", req.word.size), UVM_LOW)
endtask
endclass

endpackage

module top;
   import uvm_pkg::*;
  `include "uvm_macros.svh"
   import my_test_pkg::*;
   initial
      run_test("test");
endmodule

You could pass the values for iq and cw as parameters to the test.
Use config_db when having the comprehensive UVM topology.