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Over-verification : an intricate puzzle + sources or errors and verif processes

ben@SystemVerilog.us
ben@SystemVerilog.us
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80 posts

Interesting discussion at
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4601
ASIC design schedule +
1) Sources of errors
2) Supporting tools for the verification processes
3) Which technology(ies) provided the most benefit in reducing the verification schedule?

Ben Cohen systemverilog.us

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