In the code mentioned below,on running I get an error saying that seq from seq_top.sv is not a class item.
How do i fix this?
Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.
A similar code to the one mentioned above is given below, Can you tell me what are the differences between the 2 codes?
Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.
Thank you
In reply to Lucifer_morn :
Hi
There is issue with compilation order. i would recommend you to use package for including files. please find the link for your code with including package and corrected some minor typo in monitor,test class.
Link : Click here …
Regards,
Mitesh Patel
In reply to Lucifer_morn :
For the first example your problem is in this line:
seq.start(env.agent.seq);
You are starting a sequence /seq) on your sequencer. The sequencer object is ‘sequencer’ instead of seq.
And there is another issue. your seq_sequence does not have any members.
These assignments in your driver are causing errors:
seq.in=vif.in;
vif.out=seq.out;