Asking back that I understood right: You have N components and want to connect theit analysis ports with 1 component having N imports?
Is this correct?
Sorry ABD-91, but…
As per my understanding, we use uvm-analysis-imp-decl macro to define multiple imports in single component as we neeed to define different import function so this approach won’t work i suppose.
Hi chr-sue,
I have used this generate for connecting design signals to inteface but, how can we use this in my current scenario? Can you please give an example that who can we pass different import declarations in connect function using generate?
I did not get this running with generate, but it works with simple for-loops.
In the connect_phase I do
for (int i = 0; i < 8; i++)
mc[i].ap.connect(tc.ae[i]);
ap is an anylysis_port and ae[i] is the analysis_export/imp.