Multi level defines required

I have a case in my UVM where i have Tx and Rx agent. Both of these agents have their separate defines say TX_LANES and RX_LANES respectively,
which are used by their corresponding drivers.
But in my env there can be multiple instances of these agents , which is variable (uptil a max count say MAX_NO=4).
And these instances might have different value of TX_LANES & RX_LANES
for ex. say `AGENT_COUNT=2
AGENT1_TX_LANES = 4
AGENT1_RX_LANES = 2
AGENT1_TX_LANES = 2
AGENT1_RX_LANES = 1

So how will i do this thing in my UVM environment?

In reply to aditgupta100:

You should think about if macros are the best way to configure your UVM environment. You could do this from a test using parameters.
If you believe macros are absolutely needed you can use a macro definition file which will be included in any place you need this information. Note macros cannot be part of a package.

In reply to chr_sue:

In reply to aditgupta100:
You should think about if macros are the best way to configure your UVM environment. You could do this from a test using parameters.
If you believe macros are absolutely needed you can use a macro definition file which will be included in any place you need this information. Note macros cannot be part of a package.

I needed compile time constants args, so I used defines. Even parameter is a way but even than how will you implement multi-level parameters for my multiple-instances case ?

In reply to aditgupta100:

You can use a common package holding your parameters which is imported in all places you need this information. And you can even set them from the command line as you can do with macros.

In reply to aditgupta100:

Hello Adit,

If you want to set Tx and Rx lane numbers at compile_time go with either Macros or Parameters.

If you want to change Tx and Rx lane numbers at simulation time use $value$plusargs system task.

In reply to aditgupta100:

With parameters, you get an additional advantage of having an array of parameters.

In reply to DigvijayS:

In reply to aditgupta100:
Hello Adit,
If you want to set Tx and Rx lane numbers at compile_time go with either Macros or Parameters.
If you want to change Tx and Rx lane numbers at simulation time use $value$plusargs system task.

Yes i want to change the lane numbers at simulation time, which will be random (not necessarily from command line, it is randomized internally in uvm_sequence).

And even if you are telling me to use macros, will you maintain 16 different macros if 16 different instances (with different configuration) of Tx are required.

In reply to aditgupta100:

In that case different approaches are possible using system verilog-

One of I can think is to use dynamic array and randomize it using std::randomize() method with constraints applied to lane_numbers.



int i;
bit success;
int agent_tx; //each array element represents lane_number for particular Tx_Agent
int agent_rx; //each array element represents lane_number for particular Rx_Agent

/* Above mentioned array can be used to configure lane_numbers for each Agent */


success = std::randomize(agent_tx,agent_rx) with {
agent_tx.size==NUM_AGENT;agent_rx.size==NUM_AGENT;
foreach(agent_tx[i])agent_tx[i]>0 && agent_tx[i]<32;
foreach(agent_rx[i])agent_rx[i]>0 && agent_rx[i]<32;
};