Hi. I’m trying to write a “drive” task and getting this error in QuestaSim: “LHS in non-blocking assignment may not be an automatic variable”. Firstly at the part that i marked as:“/*****************************/” .
I have tried to create the variable “i” in interface and it did not solved.
Here is the code:
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "FSM_txn.sv"
`ifndef FSM_driver
`define FSM_driver
class FSM_driver extends uvm_driver#(FSM_txn) ;
....
task run_phase(uvm_phase phase);
FSM_txn txn ;
drive(txn);
endtask: run_phase
task drive(FSM_txn txn);
vif.data = 32'b0 ;
vif.address = 32'b0 ;
forever begin
if (vif.rst == 0 ) begin // drive address
//integer i = 31;
@(posedge vif.clock) begin
for ( int i=31 ; i>=0 ; i-- ) begin
@(posedge vif.clock) vif.address[i]= txn.address[i] ;
end
end
//check condition to drive data
if (vif.address_o == 1'b1) begin
@(posedge vif.clock) begin// drive data
for (int i=31; i>=0 ; i-- ) begin
@(posedge vif.clock) begin
vif.data[i]= t.data[i] ;
end
end
end
end
#1 // when the second case is satisfied wait along 1 clock cycle
//parity
if(vif.data_o == 1) begin
bit [7:0] address_byte3 ;
bit [7:0] address_byte2 ;
bit [7:0] address_byte1 ;
bit [7:0] address_byte0 ;
bit [7:0] data_byte3 ;
bit [7:0] data_byte2 ;
bit [7:0] data_byte1 ;
bit [7:0] data_byte0 ;
bit dummy[16:0];
for( int i=31 ; i>23 ; i--) begin
address_byte3[i-24] <= vif.address[i];/*****************************/
data_byte3[i-24] <= vif.data[i] ;
end
dummy = {^address_byte3,data_byte3} ; // now dummy[16] is parity bit of 3rd bytes (verilog concatenation)
@(posedge vif.clock) vif.parity <= dummy [16] ;
for(int i=31 ; i>23 ; i--) begin
address_byte2[i-24] <= vif.address[i-8];
data_byte2[i-24] <= vif.data[i-8] ;
end
dummy = {^address_byte2,data_byte2} ;
@(posedge vif.clock) vif.parity <= dummy [16] ;
for(int i=31 ; i>23 ; i--) begin
address_byte1[i-24] <= vif.address[i-16];
data_byte1[i-24] <= vif.data[i-16] ;
end
dummy = {^address_byte1,data_byte1} ;
@(posedge vif.clock) vif.parity <= dummy [16] ;
for(int i=31 ; i>23 ; i--) begin
address_byte0[i-24] <= vif.address[i-24];
data_byte0[i-24] <= vif.data[i-24] ;
end
dummy = {^address_byte0,data_byte0} ;
@(posedge vif.clock) vif.parity <= dummy [16] ;
end
end else begin // if rst equals to 1
#2
vif.parity = 0 ;
vif.data_o = 0 ;
vif.address_o = 0 ;
end
end
endtask : drive
endclass
`endif