Interface connection between interface pins and monitor input interface not giving value driven

UVM
1

Hello,
I have an UVM environment , where i am trying to connect driver and monitor via interface pins intf.data_in = seq and intf.data_out= intf.data_in (in driver class) and getting the intf in monitor via config_db , in driver class int.data_in and intf.data_out printing value but in monitor when i try to print intf.data_out then it gives “xxx” ,please suggest,thnks

driver part:


task run_phase(uvm_phase phase);
   forever @(posedge intf.clk) 
   begin
//  reset();
     seq_item_port.get_next_item(req);
     drive_pin(req);
     seq_item_port.item_done();
   end
endtask


task drive_pin(stimulus req);

    @(posedge intf.clk) begin 
    intf.data_in = req.data;
    `uvm_info("DRIVER",$sformatf("PIN DRIVE %h", intf.data_in),UVM_LOW)
    intf.valid = 1'b1;
    end
    intf.data_out = intf.data_in;
    `uvm_info("DRIVER",$sformatf("PIN DRIVE %h", intf.data_out),UVM_LOW)
endtask

monitor class:


function void axi_monitor::build_phase(uvm_phase phase);
begin
   if(!uvm_config_db#(virtual axi_intf )::get(this,"","intf",intf))
      `uvm_error(" ERROR MONITOR",$sformatf("%s ",this.get_type_name()))
   m_seq = stimulus::type_id::create("m_seq",this);
end
endfunction

endfunction

task axi_monitor::run_phase(uvm_phase phase);
begin
    collect_data(m_seq);
    aport.write(m_seq); 
end
endtask

task axi_monitor::collect_data(stimulus m_seq);
begin
  forever  
  begin
   @(posedge intf.clk)
   m_seq.data = intf.data_out;  
   `uvm_info("MONITOR",$sformatf("MONITOR %h",intf.data_out),UVM_LOW);
  end
end
endtask

thnks

2

In reply to ramankaur09:

There is a lot of missing information. Can you put your example on EDA Playground?

You seem to be assigning a value to ‘intf.data_out’ in your driver. Is this signal connected to an output of your DUT? If so, you will get multiple drivers and ‘X’ values.

3

In reply to cgales:

Hello,
Thank you for response.
yes,My question in simple words should be:

if we want to loopback the sequence item from driver to output interfae(no dut) and then retrieve from that output interface via get config_db , then can we access the value, because i am getting ‘x’ .
if this cant be done via interfcae then Please let me know how can we loopback data in uvm.
In system verilog we used mailboxes to transfer data