How to enable communication between uvm testbench and software executed by CPU inside DUT?
In reply to amit_p:
This is an extremely broad question. From an idealistic point of view, your testbench should only communicate with the DUT, and nothing inside the DUT. Sometimes you reach inside your DUT to speed up certain tests, but without know what you are trying to test and and how your DUT is designed, no one can answer your question.