Interface and modport

UVM
1

While accessing the signal through a modport and clocking block, is it necessary to specify clock block also?

For example,
Virtual interface is declared as:

virtual avalon_streaming_if.monitor_mp av_st_vif

The following gives error

av_st_vif.sop

The following goes through fine

av_st_vif.monitor_cb.sop
2

In reply to verif_learner:
It always helps to see the declarations of everything involved. If the modport only allows the clocking block and not the signal, you cannot access the signal directly.

3

In reply to dave_59:

Thanks, Dave. Additional code below.

interface avalon_streaming_if (input bit clk);
   logic  sop;
   logic  eop;
   ...

   clocking monitor_cb @ (posedge clk);
     input sop ... ready;
   endclocking: monitor_cb

   modport monitor_mp
   (
     clocking monitor_cb,
     input clk
   );
endinterface: avalon_streaming_if

I really did not understand what you mean by “if modport only allows the clocking block and not the signal”. Let me know if this helps.

4

In reply to verif_learner:

Your clocking block only gives you access to two identifiers: monitor_cb and clk. If you were to change your modport to

modport monitor_mp
   (
     clocking monitor_cb,
     input clk,
     input sop
   );

then you would have access to both the raw sop signal and the monitor_cb.sop signal. But one should not do this as once you introduce a clocking block, you should only access the signals through that clocking block, and not mix the two.

5

In reply to dave_59:

In reply to verif_learner:
Your clocking block only gives you access to two identifiers: monitor_cb and clk. If you were to change your modport to

modport monitor_mp
(
clocking monitor_cb,
input clk,
input sop
);

then you would have access to both the raw sop signal and the monitor_cb.sop signal. But one should not do this as once you introduce a clocking block, you should only access the signals through that clocking block, and not mix the two.

ok. actually, that really was the intention to access signal through the clock block but I assumed declaring clocking block automatically adds the signals defined the clocking block in the mod port scope.
Thanks. I think I get it now.