if my DUT is having multiple clocks and i want to consider a single active_agent in the uvm_topology.how can i declare the clocks in interface and clocking_block?
module DUT(input clk1,clk2);
endmodule
interface inif(input bit clk1,clk2);
clocking drv_cb@(clk1 or clk2);
endclocking
clocking mon_cb@(clk1 or clk2);
endclocking
endinterface
can i use like this.
In reply to mada saimanasa:
A clocking block is a SV construct which synchronizes on certain clock edges. The variables/signals can be in different clocking blocks like this
clocking cb1 @(posedge clk1);
data;
endclocking
clocking cb2 @(negedge clk2);
data;
endclocking
In this case the last clockdrive wins.
In reply to chr_sue:
can I use two clocking blocks for one driver?
interface inif(input bit clock1,clock2);
clocking drv_cb1 @(posedge clock1);
tx_data;
endclocking
clocking drv_cb2 @(posedge Clock2);
mc_data;
endclocking
endinterface
is this correct?
In reply to mada saimanasa:
Yes, this is correct. There is no limitation wrt to the clocks used in a driver. But you should carefully implement the driver functionality.