I have two interfaces, axi_vif and reset_vif, I did set these interfaces in my top module and get inside base_test. In my testcase I want to do
assign axi_vif.clk = reset_vif.aclk
but I’m getting error as virtual interfaces variables are not permitted int this context. Is there any way to do this?
Thanks!
In reply to Abuzar Gaffari:
Is this connection just for this test, or common across many tests? Why do you need to do this?
Connecting clocks is an RTL activity, especially an assign statement. This is done in the static netlist, not the dynamic testbench.
Agree with Chris here. This should be done in the RTL and not from testbench
You can do the assign axi_if.clk = reset_if.aclk assuming that the clk is declared as a wire inside the interface declaration, or if this is the only assignment to the axi_if.clk signal
You may also want to consider getting clock as an input port to the interface and driving the clocks from RTL
e.g, interface axi_if (input clk);
endinterface
Logie Ramachandran
Verikwest Systems Inc
In reply to Abuzar Gaffari:
I have two interfaces, axi_vif and reset_vif, I did set these interfaces in my top module and get inside base_test. In my testcase I want to do
assign axi_vif.clk = reset_vif.aclk
but I’m getting error as virtual interfaces variables are not permitted int this context. Is there any way to do this?
Thanks!
The assign statement is not permitted in this context.
But you should never use virtual interfaces in your test classes. This slows down the simulation speed tremendously.
In reply to chrisspear:
Yes, this is special testcase in which I am changing the clock in between the process. through registers I am changing my dut’s frequency, because of this I need to change the testbench frequency as well.
Any suggestions, solutions please?
Thanks!
In reply to logie:
Agree with Chris here. This should be done in the RTL and not from testbench
You can do the assign axi_if.clk = reset_if.aclk assuming that the clk is declared as a wire inside the interface declaration, or if this is the only assignment to the axi_if.clk signal
You may also want to consider getting clock as an input port to the interface and driving the clocks from RTL
e.g, interface axi_if (input clk);
endinterface
Logie Ramachandran
Verikwest Systems Inc
The thing is, I have one top module. Inside this top module I had included my_test.sv and without using setting and getting methods of configdb I was able to access the interface inside my testcase. but now I have removed the testcase from top module hence I am getting cross module reference error. Is there any solution for this?
sample code which was working earlier i.e before removing my testcase from top module…
module top;
`include "my_test.sv" //ToDo--Remove from here and add it in test_pkg.sv.
axi_if();
reset_if();
endmodule
my_test extends uvm_test
//Some code
assign axi_if.clk = reset_if.aclk; //If my_test.sv removed from top module then getting cross module reference error
Thanks!
In reply to Abuzar Gaffari:
Forget a moment about AXI and reset clocks.
You need to separate the concept of the clock from the value of the clock signal. The concept is that there are two separate control signals, each with unique frequency properties. Or maybe this is a control signal that has the frequency property with two different values. Think about that for a moment.
For the first case, generate two clocks and have a mux pick between then, with the select signal coming from the testbench. You could write a select_clock(A_B) function in the interface that sets the select line to A or B. Be careful as muxing clocks can cause spikes when you switch.
For case 2, create a clock generator with a frequency register. This could be just a bit for High/Low. Then make an interface function select_frequency(LO_HI) to change the delay in the generator.
This is what I did for one of my customers.
I built a quick clk_generator agent (similar to a VIP). The clk generator agent can generate any clock with different high periods and low periods. A simple sequence can set these values. This gives you full flexbility. Your clk agent can be configured by the test writer by sending a configure sequence in the middle of a test.