Identifier problem in UVM driver

UVM
1

Hello friends!

I practicing UVM with makeing i2c tests

Got a problem:
in sequence_item i made this:

class simple_transaction extends uvm_sequence_item;  
typedef enum bit {wb_write_tr = 0, wb_read_tr = 1} wb_trn_type_e;    
    rand wb_trn_type_e trans_to_wb_type;     
    `uvm_object_utils_begin(simple_transaction) 
	`uvm_field_enum	   (wb_trn_type_e, trans_to_wb_type, UVM_ALL_ON)        
    `uvm_object_utils_end
function new(string name = "simple_transaction");
        super.new(name);
endfunction     
endclass: simple_transaction

in driver i have:

.....
task run_phase(uvm_phase phase);
      fork
	reset();
	drive_item();      
      join_none
endtask : run_phase

virtual protected task drive_item();
        forever begin
          seq_item_port.try_next_item(tr_item);
            if(tr_item != null) begin           
		  case (tr_item.trans_to_wb_type)
		    wb_read_tr	: wb_read_trans;
		    wb_write_tr	: wb_write_trans;
		    default	: `uvm_error("er_type_of_tr",{"unknown transaction type", get_name()})
		  endcase
          seq_item_port.item_done(tr_item);
            end // if(tr_item != null)
            else begin
                vif.wb_dat_i <= 8'hAA;
                @(posedge vif.clk);
            end // 
        end // forever
endtask
.....

and VCS report me that:

Error-[IND] Identifier not declared
uvm/drivers/i2c_driver.sv, 57
Identifier ‘wb_read_tr’ has not been declared yet. If this error is not
expected, please check if you have set default_nettype to none. Error-[IND] Identifier not declared uvm/drivers/i2c_driver.sv, 58 Identifier 'wb_write_tr' has not been declared yet. If this error is not expected, please check if you have set default_nettype to none.

Thanks for replies,
Dmitriy

2

In reply to Levard:

Hi Levard,

Please try with following syntax[Accessing enum values using scope resolution operator].

case (tr_item.trans_to_wb_type)
simple_transaction :: wb_read_tr : wb_read_trans;
simple_transaction :: wb_write_tr : wb_write_trans;
default : `uvm_error(“er_type_of_tr”,{“unknown transaction type”, get_name()})
endcase

3

Since the definition of wb_read_tr and wb_write_tr is present inside the class, therefore the visibility of wb_read_tr and wb_write_tr is restricted to that particular class scope. As typdef is static in nature, so we can use them outside the class scope by using the scope resolution operator and without an object handle.

4

In reply to sharat:

Thanks for describing the issue !

5

In reply to Digvijaysinh Suryavanshi:

Thanks, it works!

6

In reply to Levard:

You should think about your code. Having the typedef in your definition of simple_transaction is a bad coding style. You should your typedefs etc in a package.

7

In reply to chr_sue:

In reply to Levard:
You should think about your code. Having the typedef in your definition of simple_transaction is a bad coding style. You should your typedefs etc in a package.

You mean that i have to make something like wb_agent_pkb.sv where i declare all typedef, define and include monitor, driver, seq_item and sequencer?

UPD: I made what you advice and now i don’t have earlier problem with scope resolution operator cause my enums not in any class. So important to follow good_code_style.

8

In reply to Levard:

It is a little bit different. In my UVM implementations I follow the following rule:
I define an agent related package which holds all typedefs, parameters, common methods etc.
This package can be imported in any place where you need the definitions. If you look to my homepage www.christoph-suehnel.de you’ll find an example for a complete UVM environment. This data structure has been proven in numerous projects.