How to verify override works,(when handle is father class ,inst is son class)

UVM
1

how to get inst type_name,
factory.print(); show override works,
but print_topology(); is still base_scoreboard#(T)
//print_topology();

scb base_scoreboard#(T) - @512

act_port uvm_blocking_get_port - @856

exp_port uvm_blocking_get_port - @848

------------------------------------------------------------------

//factory.print();

Factory Configuration (*)

Instance Overrides:

Requested Type Override Path Override Type

------------------- ------------- -----------------

base_scoreboard#(T) * my_scoreboard#(T)

2

In reply to designer007:

Not sure what your question is. You can always print the component hierarchy after the build phase is done and see what got constructed. UVM component hierarchy and phase ordering - EDA Playground