How to set different register map for UVM buil-in register sequences in run phase

UVM
,
1

I am trying to set different maps for UVM built-in sequence “uvm_reg_hw_reset_seq” and “uvm_reg_bit_bash_seq” as per following.

ifdef MO_ON my_seq.model.set_default_map(m_env.m_regmodel.ahb_map); my_seq.start(m_env.m_vsqr.m_ahb_sqr); else
my_seq.model.set_default_map(m_env.m_regmodel.spi_map);
my_seq.start(m_env.m_vsqr.m_spi_sqr);
`endif

But some how it is always taking all maps defined in top-level reg maps(both SPI and AHB). I have both SPI and AHB maps in my top-level maps and I use “set_default_map” in sequence to select which map I want my sequence to run with. Is it possible to select any map in UVM built-in sequences using "set_default_map ? or “set_default_map” can be used only at the build time ? Is there any way to select map for UVM-built in sequences during run-phase.