Hi,
i am New to UVM.
I have OVM test case and environment for Design and same design have the UVM environment also.
How to run the system verilog test or OVM test cases in UVM environment. if its possible?
Please guide me!!!
It is not possible. You will have to convert the OVM environment to UVM, it should not take too much effort.
In reply to dave_59:
Thank you dave_59 for replay.
for OVM class name and class library are different so it’s not possible?
then System verilog class do not have any extended class ?
In reply to santhosh1626:
That is correct. Unfortunately, backward interoperability with the OVM was not a requirement when the UVM was developed. The UVM class library was cut and paste from the OVM, it was not extended from the OVM class library.