How to pass value from one task to another in systemverilog?

Hello All,

How to pass output of one task into the input of another task in a class? I m working on monitor class in UVM. Actually I need to pass output of Serial to parallel (sipo)i.e. 10 bits(got after parallelly converting from serial input from DUT), to the input of decoder 8b10b.The 8b10b decoder takes those 10 bits as input and converts into 8bits as output. The output of decoder i.e.8 bits or a byte will then be used to form the packets back. Plz give me some guidance. Any help is appreciated.

Thanks,
Swapnil