hi sir,
i’m adpoting UVM Framework into my testbench. it’s useful and convenient, but now i met following problem.
in my testbench, i need to implement an AXI Slave agent but it seems UVM Framework does not model axi bus very well:
in driver_bfm.respond_and_wait_for_next_transfer(), bfm shall wait arvalid or awvalid, and then send the initiator data back, so that the responder/slave sequence could determine the read/write response data.
it raises following problem:
axi has seperate read/write channel, what will the bfm do if arvalid/awvalid both asserted?
and furthermore, what will the bfm do if arvalid arrives while bfm is sending previous write response data to bus?
it seems UVM Framework does not handle pipelined bus very well
thanks!