I am new to this forum and to UVM.
Hopefully one day I will be able to answer other newbies' questions too..
My sandbox practice UVM project is to verify a master SPI module.
My SPI module is actually a SystemVerilog interface in itself, so it does not need an extra inteface wrapper. I use a Driver to drive tx_data and tx_dv, and a Monitor to monitor CSN, MOSI, SCK. Driver and Monitor are in one common Agent (to make it easier with one single virtual IF handler). Monitor registers timing values, such as when CSN goes LOW, when SCK goes HIGH/LOW, when CSN goes HIGH and places them in the appropriate fields of the tx_item. A Coverage collector and a Scoreboard (Checker) watch the analysis port of the Agent. The Scoreboard prints out (to a log file) the expected timing values and the measured timing values (e.g. SCK high width, SCK low width ) and checks if they are within legal range (and constant in time).
Before Scoreboard prints the timing values and a PASS/FAIL verdict, I would like to print out the SPI words themselves too - and the coverage as it progresses from 0 to 100%.
Now, how do I print to the same log file from the Coverage collector and and the Scoreboard too?
Or, how do I transfer the coverage values from one subscriber to the other subscriber?
Must I use 'set' and 'get' with a common database? Or maybe a mailbox?
Thank you very much.
(I use EDA Playground and Xilinx Vivado if that matters.)