I am new to this forum and to UVM.
Hopefully one day I will be able to answer other newbies’ questions too…
My sandbox practice UVM project is to verify a master SPI module.
My SPI module is actually a SystemVerilog interface in itself, so it does not need an extra inteface wrapper. I use a Driver to drive tx_data and tx_dv, and a Monitor to monitor CSN, MOSI, SCK. Driver and Monitor are in one common Agent (to make it easier with one single virtual IF handler). Monitor registers timing values, such as when CSN goes LOW, when SCK goes HIGH/LOW, when CSN goes HIGH and places them in the appropriate fields of the tx_item. A Coverage collector and a Scoreboard (Checker) watch the analysis port of the Agent. The Scoreboard prints out (to a log file) the expected timing values and the measured timing values (e.g. SCK high width, SCK low width ) and checks if they are within legal range (and constant in time).
My question:
Before Scoreboard prints the timing values and a PASS/FAIL verdict, I would like to print out the SPI words themselves too - and the coverage as it progresses from 0 to 100%.
Now, how do I print to the same log file from the Coverage collector and and the Scoreboard too?
Or, how do I transfer the coverage values from one subscriber to the other subscriber?
Must I use ‘set’ and ‘get’ with a common database? Or maybe a mailbox?
Thank you very much.
Miklos
(I use EDA Playground and Xilinx Vivado if that matters.)
Hi chr_sue, I did read your reply when you posted it, sorry for the late feedback.
The problem was that I forgot the _hier postfix and my logfile was invisible from below. (I was also in a misconception about phases as to which runs when.)
In reply to mbence76:
Hi Miklos, did you solve your problem now?
Hi, in the short run: yes, I can now print my test report with coverage and test results.
In the long run I will need more sophisticated methods, but it will do for now.
Thank you.
Hi Miklos, I’m not sure if this what you are looking for a good solution is. Seeing how functional coverage increases and how many scoreboard opaertions you are doing is not really of interest. You see in the log-file only the results from 1 sequence, but you might have several hundred sequences.
What you want to see is which coverage numbers you have for all sequences and how many passes and fails you have in the scoreboard. Finally you want to measure your functional numbers against your verification plan. This is the real truth for your verification status.
See a verification plan example which can be read in to the simulator here
Hi Christoph,
you are right, seeing how functional coverage increases is not of real importance - once you are focusing on verifying the DUT and not on experiencing with how your UVM code behaves. A test report merely showing you have a 100% coverage is little protection against a faulty UVM code. That is why I would like a test report that shows step by step what is going on.
I was also thinking it might be good idea that the test report itself shows what sort of coverage it is that has reached 100%. What bins were used? How many hits were expected per bin?