Hi,
I’m stuck in the implementation where to get and print contents in scoreboard as below,
class apb_sequence_item extends uvm_sequence_item;
rand bit[9:0] address; //constraint address
rand bit[31:0] data; //constraint data
rand bit wr_en; //randomize and constraint at the sequence
bit acc;
// bit [4:0]readaddress[$];
//bit [31:0]data[$];
function new(string name="apb_sequence_item");
super.new(name);
endfunction
`uvm_object_utils_begin(apb_sequence_item)
`uvm_field_int(address,UVM_ALL_ON)
`uvm_field_int(data,UVM_ALL_ON)
`uvm_field_int(wr_en,UVM_ALL_ON)
`uvm_field_int(acc,UVM_ALL_ON)
`uvm_object_utils_end
constraint c_apb_sequence_item { data<'d40;
data>'d1;
}
constraint c_apb_address{ address<'d500;
address>'d0;
}
constraint c_apb_wr_en{
wr_en=='d1;
}
endclass
class apb_scoreboard extends uvm_scoreboard;
apb_sequence_item seq_item;
`uvm_component_utils(apb_scoreboard)
`uvm_analysis_imp_decl (_my_drv_data_imp)
`uvm_analysis_imp_decl (_my_mon_data_imp)
//add for tlm_anal_fifo test
uvm_tlm_analysis_fifo#(apb_sequence_item) tlm_fifo_exp;
uvm_tlm_analysis_fifo#(apb_sequence_item) tlm_fifo_imp;
...
virtual task run_phase( uvm_phase phase);
tlm_fifo_exp.get(seq_item);
`uvm_info(get_type_name(), $sformat("tlm_fifo_get seq_item from mon in Scoreboard : \n Address=%02h\n data=%02h\n wr_en=%02h\n acc=%02h\n %s", seq_item.address, seq_item.data, seq_item.wr_en, seq_item.acc, seq_item.sprint()), UVM_LOW)
endtask
the problem is that I’m trying to print “seq_item” each properties by using uvm_info.
But I got the error as the below
xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turnin
seq_item.address, seq_item.data, seq_item.wr_en, seq_item.acc, ), UVM_LOW)
|
*E,NOTSYF (./apb_scoreboard.sv,46|105): System task was invoked like a function (it has no return value) [2.7.4(IEEE Std 1364-2001)].
How do I get the data correctly in uvm_info?