Hi there,
I have reviewed “Training_workbook.pdf” provided in questa installation, RUVM_4.9 to be exact.
I also watched the video from verification academy presented by Tom, titled Automating the Creation of Your UVM Register Model.
The last example Tom presented had hierarchy of registers configured. Then he ran a simulation to display the details of the register model.
Being new to UVM, I need a workable example to show detail register model configuration, register names , its fields ,size,base address,offset address, reg map of a register map in detailed hierarchical way.
I appreciate very much if someone could lend a helping hand on this.
I am looking for a file, say top.sv, to be compiled, and simulated with the register model below to display in details of the register model.
Thank you in advance.
Below is the generated register model.
//----------------------------------------------------------------------
// THIS IS AUTOMATICALLY GENERATED CODE
// UVM Register Kit version 1.1
//----------------------------------------------------------------------
// Project : registers_hierarchy
// Unit : vreguvm_hierarchy_pkg
// File : vreguvm_hierarchy_pkg.sv
//----------------------------------------------------------------------
// Created by :
// Creation Date :
//----------------------------------------------------------------------
// Title : registers_hierarchy
//
// Description :
//
//----------------------------------------------------------------------
//----------------------------------------------------------------------
// vreguvm_hierarchy_pkg
//----------------------------------------------------------------------
package vreguvm_hierarchy_pkg;
import uvm_pkg::*;
`include “uvm_macros.svh”
/* DEFINE REGISTER CLASSES */
//--------------------------------------------------------------------
// Class: small_mem
//
// Small Register-Based Memory
//--------------------------------------------------------------------
class small_mem extends uvm_reg;
`uvm_object_utils(small_mem)
rand uvm_reg_field data; // Memory Cell Field
// Function: new
//
function new(string name = "small_mem");
super.new(name, 16, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
data = uvm_reg_field::type_id::create("data");
data.configure(this, 16, 0, "RW", 0, 16'hffff, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: status_reg
//
// Status Register
//--------------------------------------------------------------------
class status_reg extends uvm_reg;
`uvm_object_utils(status_reg)
uvm_reg_field reserved; // RSVD
rand uvm_reg_field ctrl_bit; // Control Bit
// Function: new
//
function new(string name = "status_reg");
super.new(name, 16, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
reserved = uvm_reg_field::type_id::create("reserved");
ctrl_bit = uvm_reg_field::type_id::create("ctrl_bit");
reserved.configure(this, 15, 1, "RW", 0, 15'b000000000000000, 1, 0, 0);
ctrl_bit.configure(this, 1, 0, "RW", 0, 1'b0, 1, 1, 0);
endfunction
endclass
//--------------------------------------------------------------------
// Class: RegA
//
// Register A
//--------------------------------------------------------------------
class RegA extends uvm_reg;
`uvm_object_utils(RegA)
rand uvm_reg_field data; // Register A Field
// Function: new
//
function new(string name = "RegA");
super.new(name, 16, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
data = uvm_reg_field::type_id::create("data");
data.configure(this, 16, 0, "RW", 0, 16'h0000, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: RegB
//
// Register B
//--------------------------------------------------------------------
class RegB extends uvm_reg;
`uvm_object_utils(RegB)
rand uvm_reg_field data; // Register B Field
// Function: new
//
function new(string name = "RegB");
super.new(name, 16, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
data = uvm_reg_field::type_id::create("data");
data.configure(this, 16, 0, "RW", 0, 16'h0000, 1, 1, 1);
endfunction
endclass
/* BLOCKS */
//--------------------------------------------------------------------
// Class: reg_block
//
// Register Block
//--------------------------------------------------------------------
class reg_block extends uvm_reg_block;
`uvm_object_utils(reg_block)
rand status_reg status_reg_h; // Status Register Instance
rand RegA RegA_h; // Reg A Instance
rand small_mem small_mem_h[8]; // Memory Instance
uvm_reg_map bus_map; // reg_block bus map
// Function: new
//
function new(string name = "reg_block");
super.new(name, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
status_reg_h = status_reg::type_id::create("status_reg_h");
status_reg_h.configure(this);
status_reg_h.build();
RegA_h = RegA::type_id::create("RegA_h");
RegA_h.configure(this);
RegA_h.build();
foreach ( small_mem_h[i] ) begin
small_mem_h[i] = small_mem::type_id::create($psprintf("small_mem_h[%0d]", i));
small_mem_h[i].configure(this);
small_mem_h[i].build();
end
bus_map = create_map("bus_map", 'h0, 2, UVM_LITTLE_ENDIAN, 1);
default_map = bus_map;
bus_map.add_reg(status_reg_h, 'h100, "RW");
bus_map.add_reg(RegA_h, 'h102, "RW");
foreach(small_mem_h[i]) begin
bus_map.add_reg(small_mem_h[i], (i * ('h2)) + ('h110), "RW");
end
lock_model();
endfunction
endclass
//--------------------------------------------------------------------
// Class: top_block
//
// Top-Level Block
//--------------------------------------------------------------------
class top_block extends uvm_reg_block;
`uvm_object_utils(top_block)
rand reg_block regs1; // Instance of reg_block
rand reg_block regs2; // Instance of reg_block
rand RegB RegB_h; // Register B
uvm_reg_map top_map; // Top-Level Map
// Function: new
//
function new(string name = "top_block");
super.new(name, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
regs1 = reg_block::type_id::create("regs1");
regs1.configure(this);
regs1.build();
regs2 = reg_block::type_id::create("regs2");
regs2.configure(this);
regs2.build();
RegB_h = RegB::type_id::create("RegB_h");
RegB_h.configure(this);
RegB_h.build();
top_map = create_map("top_map", 'h0, 2, UVM_LITTLE_ENDIAN, 1);
default_map = top_map;
top_map.add_submap(regs1.bus_map, 'h0);
top_map.add_submap(regs2.bus_map, 'h100);
top_map.add_reg(RegB_h, 'h400, "RW");
lock_model();
endfunction
endclass
endpackage