How to disable compare register while using uvm_reg_hw_reset_seq

UVM
,
1

Hi,

I have some set of register and I am using default reg sequence to check power on reset values for those register.

But I need to disable uvm_compare for some register, So I am using following method to disable some of the register

uvm_resource_db#(bit)::set("REG::",reg_model.reg1.get_full_name(),"NO_REG_HW_RESE_TEST",1)
uvm_resource_db#(bit)::set("REG::",reg_model.reg2.get_full_name(),"NO_REG_HW_RESE_TEST",1)
uvm_resource_db#(bit)::set("REG::",reg_model.reg3.get_full_name(),"NO_REG_HW_RESE_TEST",1)

While doing this I able to observe reg1 comparison is not happening (which is supposed to be) but reg2 and reg3 comparison is happening.
Even If I changed order, first register in that order is not comparing but remaining 2 still

Can anyone help on how to resolve this issue

Thanks,
Sandeep

2

In reply to Sandeep_yadav:

Hi Sandeep,

The checking(read + compare) is for all added register to the register maps, and if NO_REG_HW_RESET_TEST or NO_REG_TEST is set for any of the register then, it will skip the reading and comparison for that particular register. This skipping operation can be do for multiple registers.
Can you please paste the code for setting the attributes and sequence starting? i don’t see any issue with sequence operation.

Thanks and Regards,
Mitesh Patel

3

In reply to mitesh.patel:

Hi Mitesh,

Thanks,

I was using
uvm_resource_db#(bit)::set({“REG::”,reg_model.reg1.get_full_name(),“.*”},“NO_REG_HW_RESE_TEST”,1)

After removing .* I can able to see that check is disabled to that register.

Thanks,
Sandeep