How To create unique unpacked arrays in systemverilog

UVM
1

Hi,

I have a scenario where my data sample is 3D array. First dimension represents the controller number, Second dimension represents sample number and third dimension represents number of bits in the sample.The number of bits in a sample can vary so I had to go with unpacked array. I created the arrays as per my requirement and I need to wire a constraint in such a way that all bits for any given controller & sample are unique.

bit sample;

constraint sample_c{
foreach(sample[M]) {
foreach(sample[M][S]) {
unique sample[M][S];
}
}
}

I tried the above code. It is not working as my 3rd dimension is also unpacked array. Can you please suggest me a way even if the third dimension is unpacked array ?

Thanks,
Pavan

2

In reply to inguvapavankumar:

For me it is unclear why you need a 3-dimensional unpacked array. Please elaborate.

3

In reply to inguvapavankumar:

For me I prefer to do such unique constraint in post_processing. It’s hard to resolve the constraint if your array size is big

4

In reply to dmq0420:

Your constraint setting need 2 steps, first setting the constraint to the size of the dynamic array, secondly setting the constraint for the uniquness of the data.