Hi
I am having a little bit of confusion on creating a test plan for DUT and conclude that the DUT has been verified.
For example, if an arbiter with reset signal, two inputs(r1,r2) and outputs(g1,g2). how to create a verification plan for this.!
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In reply to sriganeshd:
Creating a test or better verification plan is not covered by the UVM. But it is an essential task in the verification process. The verification plan will be created from the requirements of the design spec (RTL). The verification plan has to define what will be verified and how do we measure design requirements are verified. We are using covergroups and assertion coverage as measuring mechanisms. An example verification plan (project proven) can be downloaded from my webpage at